Power devices have been widely used in a large number of fields such as inverters for motor control, and furthermore, power source applications for large capacity PDPs (plasma display panels), liquid crystal panels, and the like, and inverters for home electrical appliances including air conditioners and light fixtures. Conventionally, driving and control of such power devices have been performed by an electronic circuit formed of a combination of semiconductor elements such as photo couplers and electronic components such as transformers.
However, a recent advancement of a LSI (large scale integration) technology has put high breakdown voltage ICs up to 1200 V to practical use. As a result, as high breakdown voltage ICs, those including high-side gate drivers and low-side gate drivers of power semiconductor devices, further, those including control circuits and power semiconductor devices integrated on the same semiconductor substrate, and the like have been grouped. This contributes to the enhancement of efficiency of the whole inverter system, and the reduction of the component count and the mounting area.
FIG. 16 is a circuit diagram of a high breakdown voltage IC including a general level shift circuit therein. FIG. 16 is the circuit diagram of the high breakdown voltage IC obtained by adding diodes 41 and 42 to the high breakdown voltage IC shown in FIG. 7 of the following Patent Document 1. In the high breakdown voltage IC shown in FIG. 16, reference numerals 17 and 18 are IGBTs (output power devices) connected in series between the positive electrode side Vdc of a main direct-current power source of a high voltage of, for example 400 V and a common potential COM (ground potential in FIG. 16) which is on the negative electrode side of the main DC power source, and forming, for example, one phase part of a bridge circuit for power inversion of a PWM inverter.
A reference sign OUT is a connection point between an emitter of the IGBT 17 of the upper arm of the bridge circuit, and a collector of the IGBT 18 of the lower arm of the bridge circuit, and an AC output terminal of AC power generated by turning on/off of the IGBT 17 and the IGBT 18 in the complementary manner. A reference sign E2 is an auxiliary DC power source (also called a driver power source) of a low voltage of, for example, 15 V, whose negative electrode is connected to the common potential COM, and whose positive electrode is connected to a positive electrode line Vcc2. A reference sign 20 is a driver for on/off driving the IGBT 18 of the lower arm. The driver 20 operates under the auxiliary DC power source E2.
In the high breakdown voltage IC shown in FIG. 16, other circuit portion than the diodes 41 and 42, the IGBTs 17 and 18, the auxiliary DC power source E2, and the driver 20 is a level shift circuit for driving the IGBT 17 of the upper arm of the bridge circuit. A reference numeral 1 is a high breakdown voltage MOSFET for receiving an ON signal 25 of a pulse formed by a control circuit 61 (low potential side low breakdown voltage circuit), thereby to be brought into conduction. With the voltage drop of a load resistance 3 due to the conduction of the high breakdown voltage MOSFET 1 as a signal, the IGBT 17 is turned on.
A reference numeral 2 is a high breakdown voltage MOSFET for receiving an OFF signal 26 of a pulse formed by the control circuit 61, thereby to be brought into conduction. With the voltage drop of a load resistance 4 due to the conduction of the high breakdown voltage MOSFET 2 as a signal, the IGBT 17 is turned off. The control circuit 61 receives a current supplied from a low voltage power source based on the negative electrode side (the common potential COM) of the main DC power source.
Herein, the high breakdown voltage MOSFET 1 and the high breakdown voltage MOSFET 2, and the load resistance 3 and the load resistance 4 are in general formed equally to each other, respectively. Incidentally, constant voltage diodes 5 and 6 connected in parallel with the load resistances 3 and 4, respectively, have a role of restricting the excessive voltage drop of the load resistances 3 and 4, and protecting NOT circuits 8 and 9 described below. Of the level shift circuit, two high breakdown voltage MOSFETs 1 and 2 are the circuit portions for receiving signals based on the potential of the potential-fixed common potential COM.
On the other hand, the circuit portion surrounded by a broken line of FIG. 16 is a high potential side low breakdown voltage circuit portion (floating potential region) fluctuating in potential, which operates based on the potential of the AC output terminal OUT alternately following the common potential COM and the positive electrode side Vdc of the high voltage main DC power source by ON/OFF of the output IGBTs 17 and 18. A reference numeral E1 in a circuit surrounded by the broken line of FIG. 16 is an auxiliary DC power source (also called a driver power source) of, for example, 15 V, whose positive electrode is connected to a positive electrode line Vcc1, and whose negative electrode is connected to the AC output terminal OUT.
The auxiliary DC power source E1 is a power source based on the AC output terminal OUT. Further, the auxiliary DC power source E1 may be a power source based on the positive electrode side Vdc of the main DC power source when the IGBT 17 is of a p channel type. A circuit formed of NOT circuits 8 and 9, and low-pass filter circuits (which will be hereinafter referred to as LPFs) 30 and 31 at the post stage thereof, a RS flip-flop (which will be hereinafter referred to as a RS latch) 15, a driver 16, and the like operates with the auxiliary DC power source E1 as the power source.
However, the power supply voltage of the load resistance circuit formed of the high breakdown voltage MOSFET 1 and the load resistance 3, or the load resistance circuit formed of the high breakdown voltage MOSFET 2 and the load resistance 4 in which the top ends of the load resistances 3 and 4 are connected to the positive electrode line Vcc1 varies between the total sum of the potentials of the auxiliary DC power source E1 connected to the positive electrode line Vcc1 and the positive electrode side Vdc of the main DC power source, and the potential of the auxiliary DC power source E1 for the following reason: the potential of the AC output terminal OUT varies between the potential of the common potential COM and the potential of the positive electrode side Vdc of the main DC power source.
However, in actuality, reflux diodes (not shown) are connected in parallel with the IGBTs 17 and 18, respectively, with each cathode on the collector side. Whereas, by a negative voltage noise generated by the product of the induced electromotive force of the floating inductance accompanying a PCB (Printed Circuit Board) or the like, and the di/dt flowing through the IGBT, the potential of the AC output terminal OUT may become a negative value by about several tens of volts with respect to the potential of the common potential COM.
Then, a description will be given to the operation of the level shift circuit of the high breakdown voltage IC shown in FIG. 16. By the ON signal 25 inputted to the gate of the high breakdown voltage MOSFET 1, a current is passed through the high breakdown voltage MOSFET 1, resulting in the occurrence of voltage drop in the load resistance 3. When the potential of the bottom end of the load resistance 3 becomes equal to or smaller than the threshold value of the NOT circuit 8 due to the voltage drop of the load resistance 3, the output from the NOT circuit 8 becomes Hi.
A Hi level signal outputted from the NOT circuit 8 is inputted to a set terminal S of the RS latch 15 via a LPF 30, so that an output Q from the RS latch 15 becomes Hi. As a result, the IGBT 17 is turned on via the driver 16. At the same time (strictly, at a time point slightly before the ON time point for prevention of a short-circuit between the arms), the IGBT 18 is turned off by a signal from the control circuit 61 via the driver 20.
Then, by the OFF signal 26 inputted to the gate of the high breakdown voltage MOSFET 2, a current is passed through the high breakdown voltage MOSFET 2, resulting in the occurrence of voltage drop in the load resistance 4. When the potential of the bottom end of the load resistance 4 becomes equal to or smaller than the threshold value of the NOT circuit 9 due to the voltage drop of the load resistance 4, the output from the NOT circuit 9 becomes Hi.
A Hi level signal outputted from the NOT circuit 9 is inputted to a reset terminal R21 of the RS latch 15 via the LPF 31, so that an output Q from the RS latch 15 becomes Lo. As a result, the IGBT 17 is turned off via the driver 16. At the same time (strictly, at a time point slightly after the OFF time point for prevention of a short-circuit between the arms), the IGBT 18 is turned on by a signal from the control circuit 61 via the driver 20.
Incidentally, when the IGBT 18 is turned off, and the IGBT 17 is turned on, the source-drain capacitances Cds of the high breakdown voltage MOSFETs 1 and 2 are charged by a sharp potential increase dV/dt occurring in the AC output terminal OUT due to switching of the IGBTs 17 and 18. The charging current at this step causes an abnormal voltage drop different from the voltage drop due to the ON signal 25 or the OFF signal 26 during the normal operation of the level shift circuit in the load resistances 3 and 4. The abnormal voltage drops in the load resistances 3 and 4 cause the RS latch 15 to malfunction, which may erroneously turn on the IGBT 17, to entail a short-circuit between the arms of the bridge circuit, or may unnecessarily turn off the IGBT 17.
The abnormal voltage drops in the load resistances 3 and 4 may also be caused by an external noise other than being caused by switching of the IGBTs 17 and 18. The LPFs 30 and 31 are inserted in order to prevent such malfunction of the RS latch 15, and has a role of removing input signals with a small pulse width (with a high frequency) based on switching of the IGBTs 17 and 18 or an external noise as abnormal signals.
Incidentally, the reason why the IGBTs 17 and 18 are on/off driven using the ON signal 25 and the OFF signal 26 which are pulse signals as in the circuit of FIG. 16 is as follows. In order to high-speed switch AC output signals of a PWM inverter or the like, it is desirable to raise the carrier frequency for turning on/off the output switching element, and accordingly, to operate the level shift circuit at a high speed. Further, raising of the carrier frequency for turning on/off the switching element leads to a higher frequency. This can reduce the size of the coil in a power source board such as an inverter system, resulting in a merit that the PCB area can be reduced.
In order to operate the level shift circuit at a high speed, it is necessary to pass a relatively large current through the high breakdown voltage MOSFETs 1 and 2 for the level shift circuit. However, particularly when the reference potential of the high potential side low breakdown voltage circuit portion fluctuating in reference potential as the circuit portion surrounded by the broken line of FIG. 16 is at a high potential, the loss due to the current passed through the high breakdown voltage MOSFETs 1 and 2 increases.
For example, the ON current of the high breakdown voltage MOSFETs 1 and 2 is set at 10 mA; and the voltage of the positive electrode side Vdc of the main DC power source, at 400 V. Thus, if the signal for turning on the gates of the high breakdown voltage MOSFETs 1 and 2 is driven by a pulse generator, the average loss of the high breakdown voltage MOSFETs 1 and 2 when the on/off duty cycle of the high breakdown voltage MOSFETs 1 and 2 is assumed to be an average of 10% becomes a value of about 0.4 W.
Further, for example, the following Patent Document 2 describes a high breakdown voltage IC including a high-side gate driver of a power device and a level shift circuit therein. In the high breakdown voltage IC of the following Patent Document 2, for a connection between the high breakdown voltage MOSFET for level shift and a isolation island region (floating potential region), the connection is established by a wire formed on a semiconductor substrate via an insulation film. To this end, a substrate-exposed region is disposed between the high breakdown voltage MOSFET and the isolation island region. Thus, when the wire connecting the high breakdown voltage MOSFET and the isolation island region is applied with a high potential, the depletion layer expanding from the high breakdown voltage MOSFET and the depletion layer expanding from the isolation island region are joined to each other. This results in an increase in potential of the substrate-exposed region under the wire.
[Patent Document 1] Japanese Patent Publication No.
[Patent Document 2] Japanese Patent Publication No. 3917211
However, as described above, in the high breakdown voltage IC shown in FIG. 16, when the IGBT 18 is turned off, and the IGBT 17 is turned on, switching of the IGBTs 17 and 18 causes a sharp potential increase, a so-called dV/dt surge in the AC output terminal OUT. This results in a large fluctuation of the potential of the AC output terminal OUT. Further, by the fluctuation of the potential of the AC output terminal OUT, the potential of the positive electrode line Vcc1 connected to the positive electrode of the auxiliary DC power source E1 also fluctuates similarly to the fluctuation of the potential of the AC output terminal OUT.
Below, a description will be given to the malfunction caused by fluctuation of the voltage of the AC output terminal OUT and the voltage of the auxiliary DC power source E1. The high breakdown voltage MOSFETs 1 and 2 have parasitic output capacitances 51 and 52 including the source-drain capacitance Cds and a substrate-drain capacitance Cdsub as the output capacitance accounting for a large proportion of the parasitic capacitance formed upon an increase in drain potential. Upon generation of the dV/dt surge in the AC output terminal OUT, a transient current according to the dV/dt surge flows from the positive electrode side of the auxiliary DC power source E1 to the common potential COM to which the sources of the high breakdown voltage MOSFETs 1 and 2 are connected via the parasitic output capacitances 51 and 52. This results in the same state as that in which the high breakdown voltage MOSFETs 1 and 2 are apparently turned on.
When the high breakdown voltage MOSFETs 1 and 2 are put in the same state as that in which they are apparently turned on, false signals due to a displacement current are generated in the nodes connected to the drains of the high breakdown voltage MOSFET 1 on the ON signal side, and the high breakdown voltage MOSFET 2 on the OFF signal side. At this step, even when signals by the normal operation are inputted to the high breakdown voltage MOSFET 1 on the ON signal side or the high breakdown voltage MOSFET 2 on the OFF signal side, the signals by the normal operation inputted to the gates of the high breakdown voltage MOSFETs 1 and 2 do not become a transfer signal to the node of the post stage during the period in which the displacement current charges the parasitic output capacitances 51 and 52 of the high breakdown voltage MOSFETs 1 and 2. For this reason, a delay time occurs.
Whereas, a consideration will be given to the case where the parasitic output capacitance 52 of the high breakdown voltage MOSFET 2 on the OFF signal side is assumed to vary about 10% on the high side due to variations in manufacturing. In this case, by the voltage drop of the potential difference due to the product of the capacitance of the parasitic output capacitance 52, the displacement current due to the dV/dt surge, and the resistance of the load resistance 4, the potential of the bottom end of the load resistance 4 becomes equal to or smaller than the threshold value of the NOT circuit 9. As a result, a Hi level signal is outputted from the node connected to the drain of the high breakdown voltage MOSFET 2.
The Hi level signal outputted from the node connected to the drain of the high breakdown voltage MOSFET 2 is inputted to the reset terminal R of the RS latch 15 via the LPF 31. As a result, the reset terminal R of the RS latch 15 has precedence, so that the output Q from the RS latch 15 becomes Lo. Consequently, the IGBT 17 is turned off via the driver 16, which causes the high breakdown voltage IC to malfunction.
A description will be given to such a malfunction of the high breakdown voltage IC. By fluctuations of the potential of the AC output terminal OUT and the potential of the auxiliary DC power source E1 due to the dV/dt surge, the displacement current I1 transiently flows through the high breakdown voltage MOSFET 1 on the ON signal side, and the displacement current I2 flows through the high breakdown voltage MOSFET 2 on the OFF signal side. In the high breakdown voltage IC shown in FIG. 16, in order to pass a surge current to the common potential COM, diodes 41 and 42 are connected between the drain of the high breakdown voltage MOSFET 1 on the ON signal side and the AC output terminal OUT, and between the drain of the high breakdown voltage MOSFET 2 on the OFF signal side and the AC output terminal OUT, respectively.
Herein, during the potential fluctuations due to the dV/dt surge, the displacement current components flowing through the diodes 41 and 42 correspond to i1 and i2 of FIG. 16, respectively, and the displacement current components flowing through the load resistances 3 and 4 correspond to i1′ and i2′ of FIG. 16, respectively. The displacement currents I1 and 12 are expressed as I1=i1+i1′ and I2=i2+i2′, respectively.
Thus, in the high breakdown voltage IC through which the displacement currents I1 and I2 flow, first, by the dV/dt surge caused in the AC output terminal OUT, not only the potential of the AC output terminal OUT but also the potential of the positive electrode line Vcc1 to which the positive electrode of the auxiliary DC power source E1 is connected also increase with an increase in potential of the AC output terminal OUT. For this reason, immediately after fluctuations of the potentials due to the dV/dt surge, minute displacement current components i1′ and i2′ flow to the common potential COM via the load resistances 3 and 4 and the high breakdown voltage MOSFETs 1 and 2, respectively.
Then, the voltage drop due to the minute displacement current component i1′ and the load resistance 3, and the voltage drop due to the minute displacement current component i2′ and the load resistance 4 become equal to or more than the potential difference (herein assumed to be 15 V) between the positive electrode line Vcc1 and the AC output terminal OUT, and 0.6 V or more lower than the potential of the AC output terminal OUT. As a result, a current starts to flow in the forward direction of the diodes 41 and 42. Namely, in most of the displacement currents I1 and I2 upon a sharp dV/dt surge of about several tens kV/μs, the displacement current components i1 and i2 flowing along the diodes 41 and 42 become predominant. The displacement currents I1 and I2 charge the parasitic output capacitances 51 and 52 of the high breakdown voltage MOSFETs 1 and 2.
When the displacement currents i1 and i2 upon a sharp dV/dt surge of about several tens kV/μs pass along the diodes 41 and 42 to charge the parasitic output capacitances 51 and 52 of the high breakdown voltage MOSFETs 1 and 2, the voltage drop across both the ends of the load resistances 3 and 4 becomes 15.6 V or more. Accordingly, both the outputs from the NOT circuits 8 and 9 become Hi level signals. Thus, the RS latch (RS flip-flop) 15 cannot discriminate between a set signal and a reset signal. Therefore, the RS latch 15 does not accept the Hi level signals from the NOT circuits 8 and 9 as signals, so that the high breakdown voltage IC is not brought into malfunction.
However, when a gentle dV/dt surge of several kV/μs is inputted to the AC output terminal OUT, in most of the displacement currents I1 and I2, the minute displacement current components i1′ and i2′ flowing through the load resistances 3 and 4 become predominant. Accordingly, when the voltage drop due to the minute displacement current components i1′ and i2′ and the load resistances 3 and 4 results in just the vicinity of the Vth (threshold voltage) of the NOT circuits 8 and 9, the NOT circuits 8 and 9 may transfer a false signal generated by the gentle dV/dt surge to the node at the post stage.
For example, the Vth voltage of the NOT circuits 8 and 9 is caused by respective current driving abilities of a NMOS and a PMOS of a CMOS inverter formed of the NMOS and the PMOS. If the current driving abilities of the NMOS and the PMOS are assumed to be equal, the Vth voltage of the NOT circuits 8 and 9 becomes potential difference between the positive electrode line Vcc1 to which the positive electrode of the auxiliary DC power source E1 is connected and the AC output terminal OUT/2=7.5 (V).
Herein, a description will be given to the false signal generated with the displacement current components i1′ and i2′ as a trigger by taking, as an example, the case where the high breakdown voltage MOSFET 1 on the ON signal side and the high breakdown voltage MOSFET 2 on the OFF signal side are different in parasitic capacitance component from each other as described above. As described above, when a gentle dV/dt surge of several kV/μs is inputted to the AC output terminal OUT, minute displacement current components i1′ and i2′ flow between the positive electrode line Vcc1 to which the positive electrode of the auxiliary DC power source E1 is connected and the AC output terminal OUT.
When the current value of any one of the minute displacement current components i1′ and i2′ exceeds 1.5 mA (the Vth voltage of the NOT circuits 8 and 9 of 7.5 V/load resistance 5.0 kΩ), a false signal is outputted from the NOT circuit through which a minute displacement current component of 1.5 mA or more flowed of the NOT circuit 8 through which the minute displacement current component i1′ flows and the NOT circuit 9 through which the minute displacement current component i2′ flows. The false signal outputted from the NOT circuit is inputted as a Hi level signal to the RS latch 15. Accordingly, the false signal is transferred to the output Q of the RS latch 15.
Specifically, the estimates of the voltage drops on the ON-signal side and on the OFF-signal side of the false signal due to the gentle dV/dt surge are, for example, as follows.
Synthetic capacitance Cn1 of parasitic output capacitance 51 (Cds+Cdsub) of high breakdown voltage MOSFET 1:Cn1=2(pF)
Synthetic capacitance Cn2 of the parasitic output capacitance 52 (Cds+Cdsub) of the high breakdown voltage MOSFET 2:Cn2=2.2(pF)(assumed as a 10% increase due to manufacturing fluctuations)
Further, assuming that the resistance values of the load resistances 3 and 4 are respectively 5.0 kΩ, when a 0.7-kV/μs dV/dt surge is inputted to the AC output terminal OUT,
Voltage drop Vs1 of the node connected to the load resistance 3 on the ON signal side (the side through which the displacement current component i1′ flows):Vs1=2×10−12×0.7×103/1×10−6×5×103=7.0(V)
Voltage drop Vr1 of the node connected to the load resistance 4 on the OFF signal side (the side through which the displacement current component i2′ flows):Vr1=2.2×10−12×0.7×103/1×10−6×5×103=7.7(V)
Thus, the voltage drop Vr1 of the node connected to the load resistance 4 on the OFF signal side exceeds the Vth voltage=7.5 V of the NOT circuit 9. Accordingly, only the NOT circuit 9 erroneously outputs a Hi level signal.
In order to reduce such outputting of a false signal, for example, it can be considered that the resistance values of the load resistances 3 and 4 for level shift are reduced from 5 kΩ to 1 kΩ or the like. However, there is the following problem. The ON current of the high breakdown voltage MOSFETs 1 and 2 is assumed to be set at a saturation current of 10 mA when the resistance value of the load resistances 3 and 4 is 5 kΩ. In this case, when the resistance value of the load resistances 3 and 4 is 1 kΩ, a saturation current of 50 mA is required to be passed through the high breakdown voltage MOSFETs 1 and 2.
The saturation current of the high breakdown voltage MOSFETs 1 and 2 is set at 50 mA, and the voltage of the positive electrode side Vdc of the main DC power source is set at 400 V. Thus, if the signal for turning on the gates of the high breakdown voltage MOSFETs 1 and 2 is driven by a pulse generator, the average loss of the high breakdown voltage MOSFETs 1 and 2 with the collector potential of the IGBT 17 being high is about 2.0 W when the on/off duty cycle of the high breakdown voltage MOSFETs 1 and 2 is assumed to be an average of 10%. For this reason, the average loss of the high breakdown voltage MOSFETs 1 and 2 largely exceeds the allowable loss of the package for resin-sealing the high breakdown voltage IC.
Generally, even only the heat allowable loss of the SOP (Small Outline Package) enhanced in heat-dissipating capability is about 0.8 W. In order to set the heat allowable loss of the package at 0.8 W or less, the ON/OFF duty of the high breakdown voltage MOSFETs 1 and 2 is required to be reduced to 4% or less. However, when the ON duty of the high breakdown voltage MOSFETs 1 and 2 is shortened, particularly when the high breakdown voltage IC is used with a high switching frequency of from several hundreds kHz to several MHz for use in smaller-capacitance power supply equipment, the relationship with the delay time according to the input capacitance or the output capacitance of the level shift circuit, the input capacitances of the post-stage buffer circuits (such as the NOT circuits 8 and 9, and the LPFs 30 and 31) and the driver 16 may become a problem.
In the case of the high breakdown voltage IC including therein the general level shift circuit and floating potential region as shown in FIG. 16, the transfer delay time of turn ON/OFF from the load resistance circuit formed of the high breakdown voltage MOSFET 1 and the load resistance 3, or the load resistance circuit formed of the high breakdown voltage MOSFET 2 and the load resistance 4 to the driver 16 becomes about 100 ns under the influences of the parasitic output capacitances 51 and 52.
Namely, when the oscillation frequency of the high breakdown voltage IC is set at 1 MHz, the 10% duty becomes an ON period of 100 ns. This causes the restriction that the ON duty of 10% duty or less, and the OFF duty of 90% or more cannot be set. For this reason, even when driving is performed with an ON/OFF duty of the high breakdown voltage MOSFETs 1 and 2 of 4% or less in order to reduce the average loss of the high breakdown voltage MOSFETs 1 and 2, the ON signal may not be transferred according to the transfer delay time.
The signal level of the false signal generated by the displacement current due to the dV/dt surge largely depends on the capacitance values of the parasitic output capacitances 51 and 52 of the high breakdown voltage MOSFETs 1 and 2 shown in FIG. 16. On the other hand, the floating capacitance under the NOT circuits 8 and 9, the LPFs 30 and 31, and other metal wires, and the like affect the signal level of the false signal generated by the displacement current due to the dV/dt surge to a less degree as compared with the capacitance values of the parasitic output capacitances 51 and 52 of the high breakdown voltage MOSFETs 1 and 2.
Therefore, in order to reduce the displacement currents I1 and I2 causing malfunction based on the dV/dt surge while suppressing the allowable loss of the high breakdown voltage IC, it is very effective to reduce the output capacitances of the high breakdown voltage MOSFETs 1 and 2.
FIG. 17 is a plan view showing an essential part of a high breakdown voltage IC in which a level shift circuit including conventional high breakdown voltage MOSFETs and a driving circuit including a floating potential region are formed in the same semiconductor substrate. Whereas, FIG. 18 is a cross-sectional view showing an essential part of a conventional high breakdown voltage MOSFET. FIG. 18 is a cross-sectional view showing an essential part of a high breakdown voltage MOSFET for use in a conventional level shift circuit. FIG. 18(a) and FIG. 18(b) are both essential-part cross-sectional views along the cut line X-X′ of FIG. 17.
As shown in FIGS. 17 and 18, in a conventional level shift circuit, each planar shape of high breakdown voltage MOSFETs 11 and 11b which are level shift elements is laid out in a circular form. A bonding wire 201 is connected by wire bonding from the drain pad of the drain electrode 120 connected to a drain n+ region 103 formed in the center of the high breakdown voltage MOSFET 11 or 11b to the floating potential region 300.
The conventional high breakdown voltage MOSFETs 11 and 11b correspond to the high breakdown voltage MOSFETs 1 and 2 shown in FIG. 16, respectively, and are each used as a level shift element functioning as an interface between the high voltage and the low voltage of the high breakdown voltage IC called a gate driver IC. As shown in FIG. 18(a), the high breakdown voltage MOSFET 11 has the following respective regions. In the surface layer of a p− type silicon substrate 100, an n− type region 101 is formed. The surface concentration of phosphorus impurities of the n− type region 101 may be 1×1015/cm3 or more and 1×1016/cm3 or less. The depth Xj of the n− type region 101 may be 7 μm or more and 10 μm or less.
In the surface layer of the n− type region 101, selectively, a drain n+ region 103 and an n offset region 104 are formed. The n offset region 104 surrounds the drain n+ region 103. The surface concentration of phosphorus impurities of the n offset region 104 may be 1×1017/cm3 or more and 1×1018/cm3 or less. The depth Xj of the n offset region 104 may be 1 μm or more and 2 μm or less.
Further, in the surface layer of the n− type region 101, a p− well region 102 is formed. The p− well region 102 is a region surrounding the peripheral part of the n− type region 101, and connected to a ground Gnd (the common potential COM). The surface concentration of boron impurities of the p− well region 102 may be 1×1015/cm3 or more and 1×1018/cm3 or less. The depth Xj of the p− well region 102 may be 10 μm or more and 13 μm or less. The p− well region 102 is formed with a depth reaching the p− type silicon substrate 100.
Whereas, between the p− well region 102 and the n− type region 101, a p base region 105 is formed. The p base region 105 also functions as a channel region. The surface concentration of boron impurities of the p base region 105 may be 1×1016/cm3 or more and 1×1019/cm3 or less. The depth Xj of the p base region 105 may be 4.0 μm or more and 5.5 μm or less. In the surface layer of the p+ base region 105, selectively, a base pickup p+ region 113 and a source n+ region 114 of the high breakdown voltage MOSFET 11 are formed.
On the p base region 105, a gate electrode 115 of the high breakdown voltage MOSFET 11 is formed via a gate oxide film. The gate electrode 115 is formed of, for example, polysilicon. On the n− type region 101, there are formed a drain electrode 120 of the high breakdown voltage MOSFET 11 connected to the drain n+ region 103, and a source electrode 121 of the high breakdown voltage MOSFET 11 connected to the source n+ region 114.
Whereas, on the n− type region 101, there are formed a LOCOS (Local Oxidation of Silicon) 151 of a field oxide film, an interlayer insulation film 152 of TEOS (Tetra Ethyl Ortho Silicate), BPSG (Boro-Phospho Silicate Glass) or the like, and a passivation film 153 formed of a silicon oxide film and a silicon nitride film by plasma CVD.
The LOCOS 151 covers the n− type region 101 exposed between the p base region 105 and the n offset region 104. The interlayer insulation film 152 insulates the gate electrode 115, the drain electrode 120, and the source electrode 121 from one another. The passivation film 153 protects the MOS gate structure of the drain n+ region 103, the source n+ region 114, the gate electrode 115, the drain electrode 120, the source electrode 121, and the like of the high breakdown voltage MOSFET 11.
In the high breakdown voltage MOSFET 11 shown in FIG. 18(a), there are shown output capacitance components (Cds1, Cds2, and Cdsub) accounting for a large proportion of the parasitic capacitances formed upon a transient increase in drain potential of the high breakdown voltage MOSFET 11 by the sharp rise in the potential of the AC output terminal OUT due to the dV/dt surge. The input capacitance components (Cgd and Cgs) of the high breakdown voltage MOSFET 11 are about several % of the whole parasitic capacitance of the high breakdown voltage MOSFET 11, and hence, are not shown.
Of the output capacitance components shown in FIG. 18(a), the source-drain capacitance Cds includes an output capacitance component Cds1 formed of the junction of the p well region 102, the p base region 105, and the n− type region 101, and an output capacitance component Cds2 parasitic to the LOCOS 151 formed between the source electrode 121 jutting out in the direction of the drain n+ region 103 as a field plate on the negative electrode side and the immediately underlying n− type region 101.
Namely, the source-drain capacitance Cds is the total sum (Cds=Cds1+Cds2) of the output capacitance component Cds1 and the output capacitance component Cds2. As a result of performing C-V characteristic simulation under the conditions of a small signal model AC frequency of 1 MHz, the source-drain capacitance Cds when the drain potential is 30 V has a capacitance value of roughly about 0.4 pF.
Further, out of the output capacitance components shown in FIG. 18(a), the substrate-drain capacitance Cdsub is formed of the junction between the p− type silicon substrate 100 and the n− type region 101. The substrate-drain capacitance Cdsub shows the largest proportion of the parasitic capacitance components of the high breakdown voltage MOSFET 11. As a result of performing C-V characteristic simulation under the conditions of a small signal model AC frequency of 1 MHz, the substrate-drain capacitance Cdsub when the drain potential is 30 V has a capacitance value of roughly about 1.6 pF.
Further, FIG. 18(b) shows another example of the high breakdown voltage MOSFET for use in the high breakdown voltage IC shown in FIG. 17. Referring to FIG. 18(b), on an SOI (Silicon On Insulator) substrate in which on a p− type silicon substrate 100, an n− type silicon substrate 401 is formed via a silicon oxide film 200 with a thickness of several μm or more, the high breakdown voltage MOSFET 11b is formed. The p− well region 102 is formed so as to be in contact with the silicon oxide film 200.
Other regions formed in the n− type silicon substrate 401 of the high breakdown voltage MOSFET 11b are formed in the same manner as the region formed in the n− type region 101 of the high breakdown voltage MOSFET 11 shown in FIG. 18(a). Such a high breakdown voltage MOSFET 11b also has a source-drain capacitance Cds (=Cds1+Cds2) as with the high breakdown voltage MOSFET 11 shown in FIG. 18(a).
In order to reduce the output capacitance component of the high breakdown voltage MOSFET 11 forming a circular planar shape, it can be considered to reduce the PN junction area of the p base region 105 connected to the ground Gnd (the common potential COM), the p− well region 102, and the p− type silicon substrate 100, and the n− type region 101 which is a drift region (breakdown voltage region). The reduction of the PN junction area can reduce the drain-source capacitance Cds and the substrate-drain capacitance Cdsub.
However, generally, the reduction of the PN junction area formed of a region forming a circular planar shape results in the reduction of the diameter of the region forming a circular planar shape. Namely, in the high breakdown voltage MOSFET 11, the reduction of the diameter of the region forming a circular planar shape results in shortening of the drift length Ld of the drift region (breakdown voltage region). The shortening of the drift length Ld leads to the reduction of the breakdown voltage of the high breakdown voltage MOSFET 11.
This requires the reduction of only the output capacitance while keeping the diameter of the circular shape of the high breakdown voltage MOSFET 11. Also with the high breakdown voltage MOSFET 11b, there occurs the same problem that the reduction of the PN junction area results in the reduction of the breakdown voltage as that with the high breakdown voltage MOSFET 11. For this reason, also with the high breakdown voltage MOSFET 11b, there is the same problem that only the output capacitance is reduced with the diameter of the circular shape being kept as with the high breakdown voltage MOSFET 11.
Further, in the Patent Document 2, there is a description on the one in which the breakdown voltage structure of the high breakdown voltage MOSFET for level shift and the breakdown voltage structure of the isolation island region are shared in common. However, there is no description at all on those respectively forming the breakdown voltage structure of the high breakdown voltage MOSFET and the breakdown voltage structure of the isolation island region. Further, there is also no description on the output capacitance of the high breakdown voltage MOSFET.